There has been a dramatic increase in the complexity of silicon integrated circuits over the past ten years. As applications develop for microprocesses and minicomputers there is an increasing demand for greater complexities, higher switching speeds, and smaller devices in the integrated circuit. The major technology in the semiconductor process which allows this increase complexity of integrated circuits is the lithographic technology. Over the past few years only modest reductions in line widths were achieved. It has been the photolithographic defect level reductions which have allowed the high levels of integration to be achieved. There has been a gradual decrease in line widths from about 5 to 10 micrometers to about 3 to 5 micrometers at the present time. Light has been used almost exclusively until the present time in the lithographic process. However, optical resolution limits make further advances much more difficult. The thrust today is to non-light lithography, and in particular to electron beam and X-ray exposure processes to achieve the higher packing densities required for the future. These problems and their possible solutions are discussed in greater detail by B. L. Critchlow in the publication entitled, "High Speed MOSFET Circuits Using Advanced Lithography", published in the Computer, Volume 9, No. 2, February 1976, pages 31 through 37. In that publication the substantial equipment cost and complexities of X-ray and electron beam lithography are described. However, up until now it has been believed that these were the only alternatives to optical projection printing for high complexity integrated circuit devices of the future.
There have been other efforts to obtain narrow line widths in the range of 1 micrometer or less by extending standard photolithography techniques and avoiding the need to use the more expensive and complex techniques such as electron beam or X-ray lithography. One such technique is described by H. B. Pogge in IBM Technical Disclosure Bulletin, November 1976, Volume No. 6, entitled "Narrow Line Widths Masking Method." This method involves the use of a porous silicon followed by oxidation of the porous silicon. Another technique is described by S. A. Abbas, et al, IBM Technical Disclosure Bulletin, Volume 20, No. 4, September 1977, pages 1376 through 1378. This TDB describes the use of polycrystalline silicon masking layers which are made into masks by first using an intermediate mask of oxidation blocking material, such as silicon nitride in the formation of the polycrystalline silicon. Line dimensions below about 2 micrometers may be obtained by this technique.
Plasma or reactive ion etching is a technique which has been developed for etching metals, semiconductor materials and dielectrics in the manufacture of integrated circuit devices. In particular, the method of reactive ion etching which is capable of doing anisotropic etching wherein very high aspect ratios can be obtained, that is the ratio of vertical etching is much greater than the horizontal etching. The process involves the use of a plasma or ionized gas containing a variety of highly reactive particles such as ions, free electrons and free radicals. The plasmas used in etching may be maintained at relatively low temperatures of the order up to 250.degree. C. and low pressures in the range of 0.005 to 20 torr. The particles in the plasma are largely free radicals which cause the plasma's intense reactivity. The ion population in low temperature plasma is of the order of one percent of the particles. "A Survey of Plasma-Etching Processes" by Richard L. Bersin published in Solid State Technology, May 1976, pages 31 through 36 in great detail describe the plasma etching process and its application to semiconductor materials. The process has been used to make trenches or openings in silicon semiconductor bodies of various patterns as shown by Arthur K. Hochberg, U.S. Pat. No. 3,966,577 issued June 29, 1976; J. A. Bondur patent application Ser. No. 824,361 filed Aug. 15, 1977, now U.S. Pat. No. 4,604,086, and assigned to the assignee of the present patent application and J. A. Bondur, et al, patent application Ser. No. 832,856 filed Sept. 13, 1977, now U.S. Pat. No. 4,139,442, and assigned to the assignee of the present patent application. Further information about the process for reactive ion or plasma etching may be more fully understood by reference to the J. N. Harvilchuck, et al, patent application Ser. No. 594,413 filed July 9, 1975, now abandoned and continuation patent application Ser. No. 822,775 filed Aug. 8, 1977 now abandoned, and continuation patent application Ser. No. 960,322 filed Nov. 13, 1978. The RF induced plasma in the Harvilchuck, et al patent application is reactive chlorine, bromine or iodine specie. A precise description of the RF discharge apparatus and the processing is given in detail in that patent application.
Doped polycrystalline silicon have been used in place of metals such as aluminum, aluminum-copper and so forth for the ohmic contact to silicon regions. U.S. Pat. Nos. 3,664,896 to D. M. Duncan, 3,978,515 to W. J. Evans et al, and N. Anantha, et al patent application Ser. No. 844,769 filed Oct. 25, 1977, now U.S. Pat. No. 4,160,991, describe the use of polycrystalline silicon as contacts to regions in monocrystalline semiconductor devices. Published Japanese Patent Applications 50-1986, Appln No. 45-51721 (51721/70), filed June 15, 1970, inventor S. Yamazaki, and JA Patent Publication 51-36989, Application No. 45-113252 (113252/70) filed Dec. 17, 1970, inventor S. Yamazaki show, respectively, a metal insulator silicon field effect transistor device wherein the source, drain and gate electrodes are made of a conductive coating essentially consisting of the same material as the semiconductor substrate and a low doped semiconductor layer in a bipolar semiconductor transistor which acts as a conductive layer. "A 100 PS bipolar logic" by T. Sakai et al, published ISSCC '77 Feb. 18, 1977, Session XVI: High Speed Logic, pp 196 and 197 describes an elevated polycrystalline silicon electrode to be used as part of the circuit interconnection in a similar way to that of a silicon gate MOS integrated circuit. "Method for Reducing the Emitter-Base Contact Distance in Bipolar Transistors", C. G. Jambotkar, IBM TDB Vol. 19, No. 12, May 1977, pages 4601 to 4604, describes a high speed bipolar integrated circuit which uses P+ doped polysilicon for linking the base to base metallization and N+ polysilicon to link the emitter and collector reach-through metallization. It is also known to use highly doped polycrystalline silicon as the source of dopant for regions of monocrystalline silicon. The polycrystalline silicon then can either be removed or allowed to become part of the device as the contact for the region formed by the out-diffusion. These processes are taught, for example, by D. M. Duncan U.S. Pat. Nos. 3,978,515; E. Sussman 3,502,517; and in "Polycrystalline Silicon as a Diffusion Source and Interconnect Layer in I.sup.2 L Realizations" by Jan Middelhoek, et al, published in IEEE Journal of Solid-State Circuits, Vol. SC-12, No. 2, April 1977, pp. 135-138.
It is the object of the invention to extend the use of conventional lithography techniques to line widths in the submicrometer range by utilizing the plasma or reactive ion etching process to form submicrometer diffusion sources which may be used in the fabrication of highly dense integrated circuits.